library ieee;
use ieee.std_logic_1164.all;

entity mydlatch is
	port(
		d, en : IN std_logic;
		q : OUT std_logic
	);
end mydlatch;

architecture arc1 of mydlatch is
	begin 
		process (en)
			begin
				if en='1' then
					q<=d;
				end if;
		end process;
end arc1;