-- Testbench for MUX gate
library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 

architecture tb of testbench is

-- DUT component
component mux_gate is
port(
   a: in std_logic;
  b: in std_logic;
  c: in std_logic;
  d: in std_logic;
  e: in std_logic;
  s0: in std_logic;
  s1: in std_logic;
  q: out std_logic);
end component;

signal a_in, b_in, c_in, d_in, e_in, s0_in, s1_in, q_out: std_logic;

begin

  -- Connect DUT
  DUT: mux_gate port map(a_in, b_in, c_in, d_in,e_in, s0_in, s1_in, q_out);

  process
  begin
    a_in <= '1';
    b_in <= '0';
    c_in <= '1';
    d_in <= '0';
    e_in <= '1'; -- samo za testiranje redosleda dodeljivanja signala je ubacen ovaj dodatni signal e
    -- on nema veze sa multiplekserom (mux) jer je mux napravljen za samo 4 ulaza
    s0_in <= '0';
    s1_in <= '0';
    wait for 1 ns;
    assert(q_out='0') report "Fail 0/0" severity error;
  
    
    -- Clear inputs
    a_in <= '0';
    b_in <= '0';
    c_in <= '0';
    d_in <= '0';
    s0_in <= '0';
    s1_in <= '0';
    
    assert false report "Test done." severity note;
    wait;
  end process;
end tb;