Using VHDL to Describe Multiplexers

Objectives

1. Introducing Multiplexers

A multiplexer (abbreviated MUX) is a circuit that directs one of several digital signals to a single output, depending on the states of a few select inputs. We can also say that a multiplexer is a device for switching one of several signals to an output under the control of another set of binary inputs. Now let's look at the properties of a 4-to-1 multiplexer. 
	4-to-1 MUX Truth Table
	======================

		S1 S0  Y
		---------
		0  0   D0
		0  1   D1
		1  0   D2
		1  1   D3
		---------

	
	4-to-1 MUX Boolean Expression
	=============================

	Y = D0 (not S1) (not S0) + D1 (not S1) S0
	    + D2 S1 (not S0) + D3 S1 S0


	4-to-1 MUX Symbol Showing Individual lines
	==========================================
In general, a multiplexer with n select inputs will have m = 2^n data inputs. The 8-to-1 (for 3 select inputs) and 16-to-1 (for 4 select inputs) are the other common multiplexers.

Data inputs can also be multiple bits. Now let's look at the 4-to-1 4-bit Bus Multiplexer. 

	

        The Truth Table for a 4-to-1 4-bit Bus MUX
        ==========================================

                S1 S0  Y3   Y2   Y1   Y0
                -------------------------
                0  0   D03  D02  D01  D00
                0  1   D13  D12  D11  D10
                1  0   D23  D22  D21  D20
                1  1   D33  D32  D31  D30
                -------------------------
	
		Using vector notation:
		----------------------
		S = (S1 S0)
		D = (D3 D2 D1 D0)
		D0= (D03  D02  D01  D00)
		D1= (D13  D12  D11  D10)
		D2= (D23  D22  D21  D20)
		D3= (D33  D32  D31  D30)
		Y = (Y3   Y2   Y1   Y0)


	4-to-1 MUX Symbol Showing 4-Bit Bus
	==========================================
Note, in the above device symbol, the slash through a thick data line and the number 4 above the line indicates that it represents four related data signals. Similarly, an 8-to-1 or a 16-to-1 multiplexer with multiple data bus can be defined.

2. VHDL Implementation of Multiplexers

A multiplexer can be represented at the gate level in the LogicWorks. It can also be represented in a hardware description language such as VHDL. Several different VHDL constructs can be used to define a multiplexer. We can use concurrent signal assignment statement, a selected signal assignment statement, or a CASE statement within a PROCESS. We are going to briefly look into each form for a 4-to-1 multiplexer. Please note: these constructs can be extended to larger multiplexer circuits, such as 8-to-1 or 16-to-1 multiplexers.

Using Concurrent Signal Assignment Statement

Here is the general format of a concurrent signal assignment statement: 
	__signal <= __expression;
Using the Boolean expression that describes a 4-to-1 MUX in the previous section,
we can derive the following VHDL file: 
library IEEE;
use IEEE.std_logic_1164.all;


entity mux41v1 is 

 port(
		d0	: in	std_logic;
		d1	: in	std_logic;
		d2	: in	std_logic;
		d3	: in	std_logic;
		s0	: in	std_logic;
		s1	: in	std_logic;
		y	: out	std_logic
	);

end mux41v1;


architecture arch1 of mux41v1 is

begin

  -- Your VHDL code defining the model goes here
  -- Using concurrent signal assignment statement
  
  y <= (D0 and (not S1) and (not S0)) or (D1 and (not S1) and S0) or
	   (D2 and S1 and (not S0)) or (D3 and S1 and S0);

end arch1;
Although the concurrent signal assignment statement is not hard to derive, it can be very cumbersome for larger multiplexers, such as 8-to-1 MUX or greater. We may use a different statement in the architecture body.

Using Selected Signal Assignment Statement

We have learned Selected Signal Assignment Statement in the previous lab. Here is the general format for your reference: 
	__label: 

	WITH  __expression SELECT
	
	      __signal <= __expression WHEN __constant_value,
			
			  __expression WHEN __constant_value,

			  __expression WHEN __constant_value,

			  __expression WHEN __constant_value;
The 4-to-1 MUX can be described in VHDL by using Selected Signal Assignment Statement as follows: 
use IEEE.std_logic_1164.all;

library IEEE;

entity mux41v2 is 

 port(
		d0	: in	std_logic;
		d1	: in	std_logic;
		d2	: in	std_logic;
		d3	: in	std_logic;
		s	: in	std_logic_vector(1 downto 0);
		y	: out	std_logic
	);

end mux41v2;


architecture arch1 of mux41v2 is

begin

  -- Your VHDL code defining the model goes here
  -- Using selected signal assignment statement
  
  with s select
  y <= d0 when "00",
       d1 when "01",
       d2 when "10",
       d3 when "11";

end arch1;
The selected signal assignment statement evaluates the expression in the WITH clause (the 2-bit vector, s) and depending on its value, selects an expression to assign to y.

Using CASE Statement within Process

A CASE statement can be used to select among several alternatives. The expression in the CASE statement is usually a port or a signal whose value will be tested.
Here is the general format for the CASE statement within a PROCESS: 
__process_label:

PROCESS (sensitivity list)
BEGIN
  CASE __expression IS
     WHEN  __constant_value =>
	   __statement;
	   __statement;
     WHEN  __constant_value =>
	   __statement;
	   __statement;
     WHEN  OTHERS =>
	   __statement;
	   __statement;
  END CASE;
END PROCESS __process_label;
Note: The use of label above is optional.

VHDL syntax requires a CASE statement to be obtained within a PROCESS. A PROCESS is a construct containing statements that are executed if a signal in the sensitivity list of the PROCESS changes. The general format of a PROCESS is: 

[label:] PROCESS (sensitivity list)

BEGIN

        statement;

END PROCESS;
Now let's look at the 4-to-1 MUX implementation with CASE statement: 
library IEEE;
use IEEE.std_logic_1164.all;


-- define inputs and outputs

entity mux41v3 is 

 port(
		d0	: in	std_logic;
		d1	: in	std_logic;
		d2	: in	std_logic;
		d3	: in	std_logic;
		s	: in	std_logic_vector(1 downto 0);
		y	: out	std_logic
	);

end mux41v3;


architecture arch1 of mux41v3 is

begin

  -- Your VHDL code defining the model goes here
  -- Using CASE statement
  
  process(s)
  begin
  	case s is 
  	    when "00" =>
  	       y <= d0;
  	    when "01" =>
  	       y <= d1;
  	    when "10" =>
  	       y <= d2;
  	    when "11" =>
	       y <= d3; 
	    when others =>
	       y <= '0';
	end case;
  end process;
 end arch1;
If the select inputs change, the PROCESS statements are executed. The CASE statement evaluates the select input vector, s, and chooses a signal assignment based on its value.

An example of Using process structure 

 combo_Control_Outputs: process ( FSM_STATE)
     begin
          CASE FSM_STATE IS
               WHEN S0 =>
                  Cntl_Shft <= '0';
                  Cntl_Write <= '0';
                  FSM_INC_3Bit <= '0';
               WHEN S1 =>
                  Cntl_Shft <= '0' ;
                  Cntl_Write <= '1' ;
                  FSM_INC_3Bit <= '0' ;        
               WHEN S2 =>
                  Cntl_Shft <= '1' ;
                  Cntl_Write <= '0' ;
                  FSM_INC_3Bit <= '1' ;
               WHEN S3 =>
                  Cntl_Shft <= '0' ;
                  Cntl_Write <= '0' ;
                  FSM_INC_3Bit <= '0' ;
               WHEN others =>
                  Cntl_Shft <= '0' ;
                  Cntl_Write <= '0' ;
                  FSM_INC_3Bit <= '0' ;
               END CASE;
     end process combo_Control_Outputs;

3. Applications of Multiplexers

Multiplexers are used for different applications. For example, they can be used in selection of one data stream out of a group of choices (2^n, where n = 1, 2, 3, 4, ...), switching multiple-bit data from several channels to one multiple-bit output, and sharing data on one output over time.

Single-Channel Data Selection

From the introduction of the multiplexers in the first section, we can see that a multiplexer can be used to switch the select inputs to choose one data source to the multiplexer output.

Look at the following diagram, a 4-to-1 multiplexer is used to select which CD you want to play.

Multi-Channel Data Selection

Look at the following design, it is based on a quadruple (4-channel) 2-to-1 multiplexer. It will direct one of two BCD digits to a 7-segment display.
Analyse how it works.
The following 4-to-1 multiplexer selects one of the 4-bit channels and directs a 4-bit output.
For the quadruple 4-to-1 MUX indicated above, we can develop the following VHDL file: 
library IEEE;
use IEEE.std_logic_1164.all;


entity muxQ41 is

 port(
                s       : in    std_logic_vector(1 downto 0);
                d0      : in    std_logic_vector(3 downto 0);
                d1      : in    std_logic_vector(3 downto 0);
                d2      : in    std_logic_vector(3 downto 0);
                d3      : in    std_logic_vector(3 downto 0);
                y       : out   std_logic_vector(3 downto 0)
        );

end muxQ41;


architecture arch1 of muxQ41 is

begin

  -- Your VHDL code defining the model goes here
  -- Selected signal assignment
  with s select y <= d0 when "00",
                     d1 when "01",
                     d2 when "10",
                     d3 when "11";
end arch1;

Time-Dependent Multiplexer Applications

A time-dependent multiplexer application uses the multiplexer inputs channels one after the other on a repeating time sequence. Such an application can be created by applying a set of changing binary signals to the multiplexer select inputs. For example, we could connect a simple counter to the select inputs.

4. Lab Assignments

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